Contribute to several areas of product validation including functional, electrical, and stress tests. Develop validation environment, test plans, test scripts, and software to test SOC functions. Interact as needed with IP, Analog, RTL, firmware/SW and other teams to identify test requirements for SOC IOs, interfaces, and internal functions. Debug issues related to SOC fu

Gathering and synthesizing requirements for complex logic and memory structures Designing and developing complex blocks using Verilog Synthesis using Synopsys DC Place, route, timing closure using various industry standard tool flows Requirements Minimum Qualifications Candidate MUST be currently pursuing a BS/MS degree in CE/EE or related technical field(s) 0 1 years of

Develop understanding ofthe block level or chip top design for test ( DFT ) and automated test pattern generation ( ATPG ) flows for complex custom ASIC design s E xecute DFT insertion and verification flows for scan test, Memory Built in Self Test (MBIST), and IP macro test E xecute digital logic, MBIST , and IP test pattern generation and simulation flows Analyze result

Who we are Our Automotive Field Applications team is responsible for driving and supporting key design wins for Marvell's industry leading Automotive Ethernet Multi Gig T1, 1000Base T1, and 100Base T1 Switches, PHYs, and more. Who we are looking for We are looking for a customer facing, passionate, experienced, and hands on engineer physically located in the Great Detroit

Collaborat e with t est and product engineers to deliver test solutions for ASIC SoC products. Understand/influence design for test strategies and IP test methods. Specify and verify t est hardware for wafer sort and final test hardware. D evelop test plans and methodologies to meet product specifications and facilitate reuse of code/solutions across products with in a te

As a member of the MGS Design Center you will have opportunities to Work on leading edge low power high performance designs in advanced technology nodes (14nm/12nm/7nm/5nm) Work closely with other functional teams at Marvell, across IP Design, Methodology, Packaging, Test, and Manufacturing Implement multi core ARM SOCs, high speed interface designs using SerDes, PCI e, D

As a member of a dynamic development team, the candidate will be responsible for contributing to the analysis and debug of high speed DDR and SerDes IO. Participation in these tasks will allow for the candidate to gain insight into the operation of state of the art DDR and SerDes analog circuits including PLL's, Clock and Data Recovery circuits as well as Transmit FFE, Re

Manage HSM application, SDK, and firmware engineering group Recruit, grow, and manage the entire engineering team Provide mentorship and active career growth opportunities for the team Develop standards and processes to improve software security, speed, and quality Prepare, optimize and manage budgets Drive technological developments and improve efficiency Align the entir

Setup, maintain and support AMS design environment for BiCMOS/SiGe/GaAs/CMOS high speed design projects Work closely with analog design teams and EDA vendors in solving simulation related issues Collaborate with TCAD and foundry technology teams on device/circuit modeling related topics Periodically evaluate/benchmark AMS tools and present to design teams Define, develop