Collaborate withCPU architects and RTL designersto understand microarchitectural features, corner cases, and verification requirements Define and ownunit and corelevel test plans, including stimulus, checking, and functional coverage strategies Design, implement, and maintainC++based and SystemVerilogbased testbenches, with a focus onmodular, reusable verification agent a

Design and implement closed loop DVFS control subsystems on FPGA to deliver power savings while preserving timing margins across workloads. Develop power performance optimization models (e.g., Energy Delay Product) to determine optimal voltage frequency operating points for compute intensive kernels. Drive timing closure for DVFS enabled logic islands, including timing co

Innovate and develop novel Routing algorithms to get multi fold performance improvements (QoR, Compile Time, Memory Usage) Be involved in the design, implementation, analysis, and test of FPGA physical implementation tools which include optimization, placement, timing, and routing. Perform research and development of novel algorithms and optimization of existing algorithm

Innovate and develop novel Routing algorithms to get multi fold performance improvements (QoR, Compile Time, Memory Usage) Be involved in the design, implementation, analysis, and test of FPGA physical implementation tools which include optimization, placement, timing, and routing. Perform research and development of novel algorithms and optimization of existing algorithm

Collaborate with OEM/ODM partners on GPU bring up, validation, and deployment. Debug firmware, hardware, and driver issues; lead root cause investigations. Develop tools to analyze GPU performance and correlate with hardware characteristics. Optimize AI software stack across hardware and upper layers. Support manufacturing and screening tests for reliability at scale. Cre

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next generation computing experiences from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinar

Define and drive the technical strategy and roadmap for ML model optimization across AMD platforms. Serve as the highest level technical authority in performance optimization, guiding architecture, and implementation decisions. Lead performance tuning, profiling, and analysis of large scale models (LLMs, diffusion, multimodal, RecSys , generative AI) across single node an

Deep technical skills in BIOS / UEFI and FW Engineering Lead Engineer responsible for d esign ing , develop ing , debug ging , verify ing and/or validat ing firmware, software and/or hardware Support key server customers on issue repro, debugging, questions answering... Provide consultation to internal and external customers regarding AMD features and programming requirem

Act as a technical authority for PyTorch training at AMD, setting direction for performance, scalability, and reliability Drive optimization of key PyTorch training workloads (LLMs/foundation models) across single node and multi node systems Improve and debug training performance in areas such as DDP/FSDP, gradient checkpointing, mixed precision, memory planning, and comm

Drive features and functionality to our partner technical teams both internal and external including the Linux kernel community. Support the solutions offered by our partner companies. Review code, build unit tests, and write detailed documentation. Collaborate! PREFERRED EXPERIENCE Extensive expertise in x86 computing architecture Proven experience across the entire soft

Provide systems engineering and post silicon support for DDR/LPDDR/GDDR Memory interface IP. Lead Pre Silicon engagement preparing test plans, reviewing simulation results, preparing tools, automation scripts and BIOS readiness for post Si validation working closely with PHY/controller design, SI/PI, Simulation, Firmware and BIOS teams. Lead new products bring up support

Develop/Maintain tests for functional verification and performance verification at the core and SOC level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Responsible for closing verification quality metrics like pass rates, code coverage and functional coverage Provide technical support to

Work closely with Engineeringand ProgramManagersandDirectors to plan and track detailed operational and capital expenses and align budget, headcountand systems allocation Support engineering managementtoconsolidatetheir resource plans (people and materials), analyzedataand generate charts and dashboards Improve tracking, reporting, and forecasting by developing dashboards

Architecture & Platform Leadership Provide technical leadership for GPU architecture decisions with direct impact on multiASIC platforms, interconnects, memory systems, and scalability. Translate architectural concepts into concrete platform requirements spanning ASIC, firmware, drivers, and software libraries. MultiASIC BringUp Strategy Define and lead bringup strategies

Develop software in C++, Python, HIP, assembly, and SOTA programming technologies to enable key mathematical operations on GPU Design GPU computational software libraries for AI, HPC applications Aid management in planning, and delivering industry leading software for current and future processors Supervise small development team Carry out performance optimizations and pr