Build system level channel simulations to ensure packages and PCBs are designed well and meet required SI/PI specifications. Review layouts to determine any areas that require additional refinement. Extract models for package, PCB and Sockets from vendors, collecting standardized models if available, and running through simulation. Run channel simulations to generate perf

Create documentation plan and schedules based on program requirements. Produces accurate and concise technical content by leveraging knowledge of technical writing principles, resources, and advanced tools. Expertise in writing and/or editing original and highly technical user documentation, resulting in polished and professional final documentation packages for internal

Establish IP architecture project plans, milestones, and deliverables Utilize already established architecture development processes, and tangibly contributes to process improvements for higher efficiency. Creates JIRA projects & dashboards, and tracks feature development. Establish requirement to feature traceability via Jama and Jira Identifies, tracks, and mitigates pr

Complete complex mask design of analog, digital, and mixed signal circuits. Own major blocks of the custom IP designs. Direct/advise remote and local resources. Ensure all supplied data from resources are reviewed and meet milestone requirements. Schedule and forecast critical assigned blocks, maintaining schedule. Work closely with Engineering staff to ensure correct req

Manage inventory levels across multiple business units, ensuring optimal stock levels while minimizing excess inventory and carrying costs. Coordinate testing activities in laboratory environments, ensuring timely completion and accurate reporting of results. Allocate systems and resources according to the needs of various business units, balancing priorities and optimizi

Mentor and help with test and design debug, gather and update status and escalate issues to swim lane leads Tracking and updating master test plan and to detail issues in JIRA Work with Firmware, SOC Design and other Emulation engineers to debug and drive tests to completion Responsible for the design and development of test environment components to support the pre silic

Execute on RTL design and coding for various sections of the processor core pipeline and related logic. Collaborate with a team of hardware and software engineers to define the high level architecture. Participate in the definition of microarchitecture of next generation high performance processor cores. Contribute to design verification, synthesis, power reduction, timin

Driving technical innovation to improve AMD's capabilities a cross validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross functional technical initiatives Manage a high performance team of debug engineers that work directly on customer/partner systems as well as internal reference platforms Arbit

Conduct full review of existing HPC EDA infrastructure with grid, OS, and EDA tools teams as well as engineering technical leaders and re architect the future global hybrid on prem and multi cloud HPC infrastructure that is highly efficient, utilized, scalable, and cost effective. Propose innovative approaches and work collaboratively with peer teams to maximize grid perf

Drive workload and application level strategies internally and with industry partners / ecosystem. Partner with SoC design teams in providing a unified and clear platform / system level vision to influence AMDs SoC roadmap. Drive reference platform requirements and partner with engineering on balance of internal / external execution. Represent AMD datacenter system level

Be the primary point of contact for consolidating and disseminating competitive information related to AECG Adaptive SoC products, both internally and externally Develop and maintain compelling competitive collateral for AMD Adaptive SoC portfolio Provide the first line of response to sales and field teams by providing detailed competitive analysis that quantifies AMD Ada

Contribute, develop and enhance a Clang/LLVM based compiler toolchain targeting a unique VLIW architecture Take responsibility for continuous development, debugging and testing of the code you produce Collaborate closely with multiple teams to deliver key solutions to challenging, unsolved problems PREFERRED EXPERIENCE Expert knowledge and hands on experience in C++, idea

Build system level channel simulations to ensure packages and PCBs are designed well and meet required SI/PI specifications. Review layouts to determine any areas that require additional refinement. Extract models for package, PCB and Sockets from vendors, collecting standardized models if available, and running through simulation. Run channel simulations to generate perf

Lead RTL design development for USB IP blocks in Verilog HDL, make sure functional correctness, and reusability for different product lines Work in close collaboration with the design engineering teams, managers, and directors on the various efforts involved in IP development and integration Responsible for projects of significant strategies to meet AMD roadmap Responsibl

Provide compensation analysis, benchmarking, data modeling, reporting, and problem solving in support of the company's overall corporate compensation program Support administration of the merit, stock and incentive planning processes, including system testing and audit reviews of employee data Assist in communicating programs and training employees in compensation systems