Early architectural/performance exploration through micro architectural definition and design. Optimize the design to meet power, performance, area and timing requirements. Write easily readable and synthesizable Verilog RTL. Run some unit level testing to deliver quality code to the Design Verification Team. Create assertions to improve coverage and cover points to analy

Technical Leadership Own systemlevel performance attainment and HW/SW optimization to improve out of box and sustained performance across silicon products. Lead post silicon debug, regression, performance analysis, and optimization efforts to achieve committed product targets. Establish and evolve methodologies for power and performance modeling, validation, and siliconbr

Optimize Deep Learning Frameworks Enhance and optimize frameworks like TensorFlow and PyTorch for AMD GPUs in open source repositories. Develop GPU Kernels Create and optimize GPU kernels to maximize performance for specific AI operations. Develop & Optimize Models Design and optimize deep learning models specifically for AMD GPU performance. Collaborate with GPU Library

Responsibilities may include a subset of the following topics Drive PVT corners/ frequency targets while considering various product performance modes and guard bands Drive IP physical implementation recipes from synthesis to route to achieve the best performance/watt RTL (architecture) and PD co development to identify bottlenecks Drive budgeting, measurement, analysis a

Lead AMD's global TMS strategy, architecture, and multiyear roadmap. Drive the full TMS vendor selection process, including requirements, RFP execution, evaluation, and final recommendation. Serve as the program lead for global TMS implementation, integration, and deployment across regions and transportation modes. Partner with IT and technology vendors on system design,

We are seeking a skilled and dedicated Server Platform SoC Validation lead and Debug Engineer to join our Server Platform Solution Engineering Group's Debug team. In this role, you will work on cutting edge server EPYC and AI Platforms to lead validation and debug to meet the program milestones. Your responsibilities will include collaborating with Platform architecture,

Verification Architecture Define scalable mixed signal verification architectures for advanced analog digital subsystems. Establish signoff criteria, coverage models, and closure frameworks across concurrent silicon programs. Integrate digital UVM based environments with analog/mixed signal modeling strategies (real number modeling, AMS co simulation, abstraction framewor

Strategy & Program Leadership Contribute to the development and execution of AI Education and Developer Outreach Marketing strategy in alignment with broader AI and marketing priorities. Own defined program areas within AI education outreach marketing for non academic and academic communities, and early pipeline initiatives, ensuring high quality execution and measurable

Manage New Requisition process check for accuracy, route for approvals Service Central Tickets respond to questions from candidate/employees on TA Process Employee Referral Program Process payment submissions and assist with employee/recruiter questions General project management updating TA One Note, process documentation, training, and other projects HR Technology forum

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next generation computing experiences from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinar

Cluster Bring up & Optimization Oversee the technical onboarding of massive GPU clusters. Ensure your team can troubleshoot collective communication errors, debug framework issues, andoptimizetraining/inference strategies. UtilizationEngineering (The North Star Metric) Drive andmaintainindustry leadingCustomer GPU Utilizationacross clusters of thousands of GPUs, making cl

Interface with silicon, power architect, firmware and platform team to close power management feature evaluation in pre silicon phase Key stakeholder for pre silicon power/perf projection Develop test plans for post silicon power management feature tunning and power charz Post silicon power management feature tuning to optimize power and performance Post silicon power cha

To mentor sub block owners and conduct peer reviews of design and verification results To work with pre tapeout verification and post silicon validation teams to bring up silicon and analyze silicon results PREFERRED EXPERIENCE To own macro level high speed clocking system for ultra high speed electrical and optical transceivers reference clock, PLL, buffers and muxes, di

Own the AI Developer Digital Journey In tight collaboration with key stakeholders, define and lead the strategy for the end to end developer journey across AMD.com and connected platforms (developer portals, community forums, learning hubs, and AI ecosystem touchpoints). Accelerate AI Developer Growth Create targeted digital experiences and engagement strategies to attrac

Define circuit architectures optimized for high bandwidth electrical and optical links Perform link level simulation in Matlab and/or SPICE to prove the architecture Perform design and modeling of on die RF passive components (e.g., inductors and capacitors) and/or optical structures Design circuit components (e.g., DAC, SAR ADC, S/H, Analog Front End, PLL, reference gene