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Perform Functional verification of high speed Microprocessor designs, including development of infrastructure, directed and random test suites at behavioral RTL and gate design levels across SoC, Core and block hierarchies. Develop environments, infrastructure, and test plans to accommodate both full chip and stand alone block level verification and debug capabilities usi
Posted 5 days ago
Establishes and maintains AMD's technological leadership position Considered technical leader across project and departmental boundaries and has a proven track record for sustained innovation. Is responsible for projects or processes of significant strategic or commercial importance and for project/program results Deals with problems requiring cutting edge approaches and
Posted 5 days ago
The primary objectives of this role are Lead strategic ecosystem initiatives in connectivity software (e.g. WLAN, Bluetooth, WWAN stacks and middleware), enabling best in class PC platform connectivity experience based on AMD technology Collaborate with AMD cross functional teams (engineering, product management, segment marketing, sales, customer engineering) to drive ec
Posted 6 days ago
include FPGA design using Verilog RTL FPGA verification using simulators FPGA Synthesis/Place/Route using Vivado FPGA debugging on the hardware Required to come onsite to the San Jose office located at 2100 Logic Dr San Jose, CA 95124. Duration 4 months, full time (40 hours per week) Expected start date January 2023 Education Currently enrolled in EE/CS Graduate or Undergr
Posted 8 days ago
What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD
Posted 8 days ago
Register transfer level (RTL) performance analysis and microbenchmarking for the Infinity Fabric memory system composed of the Interconnect and Memory Controller. Work closely with the architecture, design, and modeling teams working on high performance systems on chip (SOC) memory system designs. Execute on microbenchmarking plans at the IP level, and support performance
Posted 8 days ago
Identify potential issues, summarize the facts and background, explore possible alternatives or resolutions, and suggest a course of action Gather financial data and perform financial analyses and reporting Analyze trends within the business and ensure alignment with business and corporate objectives Interact with a wide range of business professionals throughout AMD Prio
Posted 8 days ago
Create microarchitecture and write RTL Verify intended functionality with block /unit level test bench and coordination with other teams Write optimal timing constraints (SDC) Run design sanity checker tools such as LINT, CDC, FishTail, etc. Work closely with physical design team during implementation Document designs and use effective verbal communications PREFERRED EXPE
Posted 8 days ago
Perform Functional verification of high speed Microprocessor designs, including development of infrastructure, directed and random test suites at behavioral RTL and gate design levels across SoC, Core and block hierarchies. Develop environments, infrastructure, and test plans to accommodate both full chip and stand alone block level verification and debug capabilities usi
Posted 8 days ago
High speed VLSI design in deep submicron FinFET processes. Work closely with chip architects and designers across multiple sites to optimize power, performance, area, and schedule. Solve design and tool problems requiring ground breaking approaches and champion innovation across the organization. Create technical presentations for peers and management. PREFERRED EXPERIENC
Posted 8 days ago
As a member of this talented high performance team the selected candidate will be responsible for developing innovative new product features designed to enable customers to build ever more complex systems faster and easier. He or she will be involved in all aspects of product development; design, prototyping, implementation, testing, and productization. The IP Integrator
Posted 8 days ago
Create block level verification plan, test plans and full chip test plan Develop block level test bench and tests in UVM methodology including scoreboard. Work on subsystem level verification Work with designers to get the coverage closure Port the block level tests to full chip test bench Integrate VIPs as needed Work with software, validation and emulation teams as need
Posted 8 days ago
Technical lead for high speed VLSI design in deep submicron FinFET processes. Work closely with RTL and physical designers across multiple sites to optimize power, performance, area, and schedule. Solve design and tool problems requiring ground breaking approaches and champion innovation across the organization. Create technical presentations for peers and management. Gui
Posted 8 days ago
As a Domain Engineer, you will work on all aspects of SOC validation from pre silicon planning and emulation, to post silicon Power On, Validation, and Debug. The focus will be on the validation of high speed I/O interfaces (USB, PCIE, GMI, LPDDR / DDR, I/O Controllers), targeting their SOC/PHY level functionalities and interactions in unique system topologies. Responsibi
Posted 8 days ago
Perform functional feature verification of high speed Microprocessor designs, including development of infrastructure, directed and random test suites at behavioral RTL level across SoC, Core and block hierarchies. Develop environments, infrastructure and test plans to accommodate both full chip and stand alone block level verification and debug capabilities using simulat
Posted 8 days ago
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