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Design Verification (Performance) Engineer
Austin, TX
Job Description
Design Verification (Performance) Engineer
Location: AUSTIN (US:73301), TX
Hybrid role
Expectations include:
* The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities.
* The test cases should cover system scenarios/ benchmarks which stress target path/ feature as well as subsystem analysis.
* The reference metrics to qualify the results needs to be synthesized based on references from system architecture team, software team, IP team, industry standards or defined based on abstract use case descriptions available as part of design requirements.
* Strong skills in debug, failure re-creation and root cause analysis
* Work with peer teams to correlate performance metrics across different platforms (TLM, RTL, Emulation, Silicon validation, applications).
* Working with cross domains - IP owners, Systems and Core design teams to achieve performance verification objectives.
Job Qualifications
Experience in below areas is needed
* Experience with HDL/HVL like Verilog, System Verilog, VIP monitors, UVM methodology.
* Strong understanding Bus Protocols like AHB, AXI, NIC, ACE, NOC.
* Understanding of processor architecture, debug architecture, Cache Coherency
* Understanding of memory subsystems, caches, DDR controllers.
* Programming skills in C/C++/ Python or other languages.
* User experience to execute, analyze and debug test cases on emulation platform would be an added advantage.
* Domain knowledge in at least some of the areas like Graphics/Multimedia/Networking IPs like PCIe, MIPI, Ethernet, USB etc
System Verilog/UVM/Python/C/C++
Ampcus is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identify, national origin, age, protected veterans or individuals with disabilities.
Location: AUSTIN (US:73301), TX
Hybrid role
Expectations include:
* The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities.
* The test cases should cover system scenarios/ benchmarks which stress target path/ feature as well as subsystem analysis.
* The reference metrics to qualify the results needs to be synthesized based on references from system architecture team, software team, IP team, industry standards or defined based on abstract use case descriptions available as part of design requirements.
* Strong skills in debug, failure re-creation and root cause analysis
* Work with peer teams to correlate performance metrics across different platforms (TLM, RTL, Emulation, Silicon validation, applications).
* Working with cross domains - IP owners, Systems and Core design teams to achieve performance verification objectives.
Job Qualifications
Experience in below areas is needed
* Experience with HDL/HVL like Verilog, System Verilog, VIP monitors, UVM methodology.
* Strong understanding Bus Protocols like AHB, AXI, NIC, ACE, NOC.
* Understanding of processor architecture, debug architecture, Cache Coherency
* Understanding of memory subsystems, caches, DDR controllers.
* Programming skills in C/C++/ Python or other languages.
* User experience to execute, analyze and debug test cases on emulation platform would be an added advantage.
* Domain knowledge in at least some of the areas like Graphics/Multimedia/Networking IPs like PCIe, MIPI, Ethernet, USB etc
System Verilog/UVM/Python/C/C++
Ampcus is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identify, national origin, age, protected veterans or individuals with disabilities.
Job Summary
Company
Start Date
As soon as possible
Employment Term and Type
Regular, Full Time
Required Experience
Open
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