46597BR
USA - Massachusetts - Boxborough, USA - USA
Job Description and Requirements
The Digital Implementation team is seeking a highly motivated and innovative engineer who be part of the timing team working on timing flows, constraints, analysis & debug of timing issues that will enable physical design activities and will be responsible for physical design implementation of the Mixed-Signal DDR PHY IPs in various cutting edge process technologies. In this role you will work on a variety of advanced DDR PHY developments including the latest standards in LP5x and DDR5. The position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers.
Physical Design Engineer
Key Responsibilities:
Tasks will include but not be limited to, scripting, debugging, testing and maintaining of timing flows and methodologies, documentation, synthesis, Place & Route, Static timing closure, constraints analysis, static and dynamic IR drop analysis, power estimation, electromigration checks and other physical verification tasks such as DRC/LVS/ERC.
The candidate will be expected to work independently to find solutions to complex design implementation issues and to analyze and suggest improvements to the design methodology and design flow.
Additional tasks will include creation of views necessary for SOC integration of the hard macros and running all required QA checks before release of these views.
Key Requirements:
A degree in Electrical/Electronic Engineering (or equivalent) with 3+ years of digital or physical design experience. Master's degree is preferred.
Job Category
Engineering
Country
United States
Job Subcategory
ASIC Physical Design
Hire Type
Employee
Base Salary Range
$97,000-145,000