Senior level DFT Engineer
Santa Clara, CA 
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Posted 13 days ago
Job Description
About Marvell

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform-for the better.


The data infrastructure that our customers build has never been more critical to our global economy. It's what's keeping the world connected, businesses running, and information flowing. If you're ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Switch DFX team is responsible for overall DFT solution implemented in all Marvell Switch products. The team owns DFX Strategy, DFX Architecture, DFX IP's and all aspects of SoC MBIST and ATPG definition, implementation, validation pre and post-Si.

Job Responsibilities:

As a part of the DFT team the suitable candidate will work on all aspects of DFT in top notch Switch products: DFT architecture and Testability strategy, Flow, Implementation, Verification and post Si bring up.

You'll work closely with other DFT team members for DFT features Implementation, Integration and Verification in SoC. You will also have close interaction with Logic Design/Physical design/STA/ATE teams as needed.

Requirements:

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
Master's degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience.
PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.

The ideal candidate Marvell will have the following or relevant experience

  • Very good knowledge on SCAN/ATPG/JTAG/MBIST

  • Proven experience on gate level simulations with notiming and SDF based simulations for DfT modes

  • Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques

  • Proven experience in Scan insertion techniques at block level and Chip top level

  • Good knowledge on Test mode timing constraints

  • Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team

  • Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools)

  • Good Knowledge and understanding on JTAG for IEEE1149.1/6 standards

  • Experience with Post-Si ramp up and debug on ATE

  • Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level

  • Good knowledge on Perl/ Tcl scripting skills.

  • Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization

  • High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project

#LI-KB1

#LI-HYBRID

#LI-ONSITE

The Perks

With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We'll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.

Your Future

Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.

At Marvell, we are doing our part to help keep our communities and our teams safe. As part of our efforts to address the Covid pandemic and future epidemics, you may be required at any time by our policies or applicable laws to provide proof of applicable vaccination or to present negative test results.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at or 408-222-3604.

 

Job Summary
Start Date
As soon as possible
Employment Term and Type
Regular, Full Time
Required Education
Bachelor's Degree
Required Experience
15+ years
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