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SOC Timing/ EMIR Analysis Methodology Engineer 178161
The AMD AEComputing Methodology team is seeking an experienced engineer to help investigate, develop, and deploy new techniques to optimize and analyze SOC timing and power to help create the next generation of Adaptive and Embedded silicon products including FPGA, APUs, DPUs, AIE and IO subsystems, Monolithic and 3D SOCs to give unparalleled flexibility to AMD customers. AMD is looking for a strong candidate who can bring in disruptive ideas that will ensure that AMD silicon is best in class.
As a member of our team, you'll be responsible for collaborating with experts across various aspects of the SOC design flow, including, but not limited to Physical Design, Timing Closure, EMIR analysis, Power analysis to tape-out in the most advanced process nodes. In our group, your work will have widespread and immediate impact on the ongoing projects.
You are a forward-thinking self-motivated engineer who continuously works to optimize/improve the workflow, anticipates technical issues, has deep analytical and problem-solving skills, and enjoys a competitive pace. In addition, you have strong written and verbal skills, strong presentation skills, strong problem-solving skills, and have an exceptional attention to detail.
San Jose, California
Requisition Number: 178161
Country: United States State: California City: San Jose
Job Function: Design
Benefits offered are described .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click for more information.