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We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

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THE ROLE:

As the leader of the Fabric Configuration team in the US for AMD's Adaptive-Embedded Computing products, you will be responsible for driving the development of FPGA Configuration solutions that meet the high standards of AMD's AECG products. This will involve leading a team of highly skilled engineers in the US, as well as collaborating with partner design teams in other locations, inventing and implementing original solutions, addressing challenging FPGA Configuration problems in some of the industry's largest and most complex SOCs.

Every new Adaptive SOC brings a new set of Configuration challenges with their latest system and functional architectures and their adoption of new semiconductor and packaging technologies. The Fabric Configuration team works closely with functional Architecture, Silicon Technology, Security, Programable Fabric, Integration, Product Engineering and SW teams to craft and implement HW/SW solutions and deliver Configuration IP for fullchip integration.

THE PERSON:

This is a critical role within the company, and requires a combination of technical expertise, leadership skills, and effective communication. If you are passionate about system and circuit design and have a track record of leading successful teams, this could be an exciting opportunity for you to join an innovative team at AMD.

You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging circuit and system problems.

KEY RESPONSIBILITIES:

• Developing robust and efficient FPGA Configuration solutions for AMD's next generation of programmable product families.
• Working with Chip, Functional and Security Architects to define Configuration methodologies covering existing and future protocols.
• IP definition, Micro-Architecture, RTL and circuit design; timing, electrical and physical verification at block and full-chip levels.
• Close cooperation with Silicon Technology, Functional Verification and Integration teams.
• The team is responsible for multiple analog and digital blocks which interact both intra-die and inter-die, in the case of multi-chip solutions.
• Direct and assist the team to implement all stages and functions of design flows from database setup, CAD support, Timing and Verification tools and Silicon Validation and Characterization.
• Actively manage team's goals, dependencies and milestones.
• Lead and develop the team: The candidate should provide the necessary training and development opportunities to help the team grow and succeed.

PREFERRED EXPERIENCE:

• You should have a deep understanding of digital design at the block and system level, as well as experience in leading teams to deliver complex projects. Working knowledge of mixed signal circuits and memory cell design is a plus.

• The Configuration solution is a critical part of overall chip yield, reliability, performance and power, and understanding the chip-wide implications is key. System level expertise is essential to leading cross functional teams to an optimal solution.
• Experience with micro-architecture, RTL coding, Circuit, Layout design process and silicon tapeout criteria sign off.
• Familiarity with test, debug, yield, post-Silicon Validation & Characterization is required.
• Proficiency in STA and methodologies for timing closure and a good understanding of noise, cross-talk, Aging and OCV effects, among others.
• Familiarity with EDA tools, Design Compiler, ICC2, Primetime. Working knowledge of extraction and STA methodology and tools.
• Familiarity with circuit modeling, including SPICE models, and worst-case corner selection.
• Familiarity with Verilog and system Verilog for design.
• Familiarity with FPGA design suite including but not limited to Vivado and Vitis.
• Solid understanding of scripting languages such as Perl/Tcl. Knowledge of python is a plus.
• Additionally, you should be a skilled communicator, able to provide technical guidance and mentorship to your team members and to help resolve cross functional issues with other teams in an efficient manner.
• Comfortable working across geographies, particularly India, Singapore and US.

ACADEMIC CREDENTIALS:

• BS, MS or PhD in Electrical and/or Computer Engineering, Computer Science or related field.

LOCATION: San Jose, CA

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At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD's Employee Stock Purchase Plan. You'll also be eligible for competitive benefits described in more detail .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.