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SOC Timing/ EMIR Analysis Methodology Engineer 178161

THE ROLE:

The AMD AEComputing Methodology team is seeking an experienced engineer to help investigate, develop, and deploy new techniques to optimize and analyze SOC timing and power to help create the next generation of Adaptive and Embedded silicon products including FPGA, APUs, DPUs, AIE and IO subsystems, Monolithic and 3D SOCs to give unparalleled flexibility to AMD customers. AMD is looking for a strong candidate who can bring in disruptive ideas that will ensure that AMD silicon is best in class.

As a member of our team, you'll be responsible for collaborating with experts across various aspects of the SOC design flow, including, but not limited to Physical Design, Timing Closure, EMIR analysis, Power analysis to tape-out in the most advanced process nodes. In our group, your work will have widespread and immediate impact on the ongoing projects.

THE PERSON:

You are a forward-thinking self-motivated engineer who continuously works to optimize/improve the workflow, anticipates technical issues, has deep analytical and problem-solving skills, and enjoys a competitive pace. In addition, you have strong written and verbal skills, strong presentation skills, strong problem-solving skills, and have an exceptional attention to detail.

KEY RESPONSIBILITIES:

• Analyze existing PD, Timing and EMIR flows and methodologies and identify weaknesses and areas for improvement
• Tuning the design flows to achieve optimal power, performance, area and turnaround time on a range of designs spanning FPGA, AIE, APU, DPU cores, NOC, SOCs and 3D
• Partner with design, technology and architecture teams to drive changes that improve PPA and TAT
• Coordinate the efforts of physical design, timing and EMIR engineers, CAD engineers, and EDA vendors to deliver a leading edge, SOC design methodologies
• Solve design and tool problems with ground-breaking approaches and champion innovation across the organization
• Foster collaboration and knowledge sharing through technical presentations towards peers and management

PREFERRED EXPERIENCE:

• VLSI Circuit Design and ASIC design flow
• High Speed logic design and synthesis
• Timing Analysis and Optimization
• Electromigration and IR Drop analysis
• Low Power design Techniques
• Tool Driven Place and route
• Experience with Physical design and analysis tools such as ICC2, Primetime, Nanotime, Redhawk, Totem
• Experience with tool scripting Perl, Python and TCL are preferred
• Excellent communication skills (both written and oral)
• Self-motivated, and committed to achievement

ACADEMIC CREDENTIALS:

• BS/MS in Computer Science, Computer Engineering, Electrical Engineering or related

LOCATION:

San Jose, California

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Requisition Number: 178161
Country: United States State: California City: San Jose
Job Function: Design

Benefits offered are described .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click for more information.