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Candidate will be responsible for characterization methodology across multiple subjects. These will span speed and stress testing of DDR chip to chip and HBM interfaces, power distribution disturbance by step loads, and signal disturbance by proximity and phase of aggressors.

Key Responsibilities:

• Define PDN test methodology/strategy for all IP
• Define SSN test methodology/strategy for I/O
• Define Memory Controller data traffic for worst SI/PI effect
• Work with design to come up with optimum settings for Memory system settings (eg: I/O, Vref settings)
• Provide guidance to AMD-SG SI/PI engineer for SI/PI test executions

Qualifications:

• BS + 9 years or
• MS + 7 years or
• PhD + 5 years

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Requisition Number: 175402
Country: United States State: California City: San Jose
Job Function: Design

Benefits offered are described .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click for more information.